Verkor

Chip design's final frontier

Featured in IEEE Spectrum, Tom's Hardware

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Verkor's autonomous agentic system, Design Conductor ("Conductor" for short), applies the capabilities of frontier models to build semiconductors end-to-end -- from concept to verified, tape-out ready GDSII (layout CAD).

We see a future in which humans spend their time providing expert architectural and design input to Conductor, enabling very fast design iteration and time to tape-out.

Design Conductor has autonomously built several designs, including VerTQ, an LLM attention accelerator which hard-wires Google's TurboQuant KV compression algorithm. This design, containing 5129 custom floating-point units, was built and mapped to an FPGA by Design Conductor over ~80 hours. Design Conductor also build VerCore, a 1.5 GHz Linux-capable RISC-V CPU, with its only human input being a 219-word requirements document. VerCore achieved a CoreMark score roughly equivalent to that of an Intel Celeron SU2300 from mid-2011.

Read the full technical report describing several designs built by Design Conductor 2.0: https://arxiv.org/abs/2605.05170. Read the full technical report describing how Conductor built VerCore at https://arxiv.org/abs/2603.08716.

VerTQ physical layout across three SLR dies of an XCVU29P-3 FPGA.
VerTQ Physical Layout in 4-die XCVU29P-3 FPGA. 3x SLR dies shown. Conductor 2.0 optimized the architecture to minimize inter-die signal crossings.
Physical layout of an AES core in the ASAP7 7nm PDK.
Physical layout of 400Gbps AES core built by Design Conductor in ASAP7 7nm PDK.

Verkor is working with multiple of the top 10 fabless companies to deploy Conductor to accelerate their time to market.

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To get in touch, contact us at team@verkor.io.